1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a failed row or column in a memory array including a failed memory cell is electrically replaceable by a redundant row or column, respectively. The invention also relates to a method of electrically confirming a failed memory cell in such a memory device.
2. Description of the Background Art
The semiconductor memory device has so far suffered a problem that the production yield tends to be lowered due to defects, such as a failed memory cell, or breakage or short-circuiting of a word or bit line. The conventional practice to cope with this problem has been to provide a redundant memory cell array including redundant memory cells in advance on the semiconductor chip, in addition to the regular memory cells 41, so as to electrically replace a failed row or column including the failed memory cell by the redundant row or column, respectively.
With such a semiconductor memory device, there is no solution for electrically confirming the address of a row or column including a failed memory, i.e. “failed address”, to be replaceable by a redundant row or column. Such a solution has been demanded, heretofore.
A solution for electrically confirming a failed address in a semiconductor memory device is disclosed, for example, by Japanese patent laid-open publication No. 203296/1996, in which a semiconductor memory device including a voltage dropper circuit. In the solution, when a redundant row or column is selected to replace the regular row or column, respectively, the semiconductor memory device is run in operation not by the decreased power supply voltage but by an external power supply voltage. Thus, a measurement of the power supply current or the access time would make it possible to verify whether or not the redundant row or column has been selected.
However, the solution disclosed in the Japanese publication has a problem that it inherently involves an analog fuzziness in the verification.